1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a clock gated circuit including a transistor that prevents unnecessary electric charge from inflowing into a “fighting node” to reduce power consumption and discharging time.
2. Description of the Related Art
In one semiconductor chip, a plurality of blocks can be included according to the function of the semiconductor chip. FIG. 1 is a schematic block diagram of a semiconductor chip including a plurality of blocks. Referring to FIG. 1, the semiconductor chip 100 includes four blocks B1 through B4. The four blocks B1 through B4 are synchronized with one clock signal CLK during operation.
However, in contrast to the current trend that requires low power, activation of unnecessary blocks causes a waste of power. In particular, with the decreased size of semiconductor chips, power consumption due to leakage of power has been a cause of trouble, rather than power consumption due to power consumption during operation. Thus, various methods to prevent power consumption have been introduced to overcome such a problem. One of the methods employs a clock gated circuit. The clock gated circuit includes a latch circuit and is called a clock gating latch positive circuit (CGLP).
FIG. 2 is a timing diagram conceptually illustrating an operation of a clock gated circuit in accordance with the prior art.
Referring to FIG. 2, while an enable signal EN is activated, the clock gated circuit generates a gated clock signal GCK which is synchronized with a clock signal CLK. When the enable signal EN is transitioned, that is, deactivated, to logic low L at a predetermined time t, the gated clock signal GCK has a value of logic low L. In this case, a block corresponding to the enable signal EN is charged into a sleeping mode so that the block can be deactivated when the block is not in an active mode.
FIG. 3 is a diagram illustrating a general clock gated circuit in more detail, in accordance with the prior art.
FIG. 4 is a timing diagram illustrating an operation of the clock gated circuit of FIG. 3 during a discharging operation, in accordance with the prior art.
An operation of the clock gated circuit 300 in a section where an enable signal EN is activated will be described with reference to FIGS. 3 and 4. When the enable signal EN is activated with logic high H, second and third NMOS transistors N2 and N3 are turned on.
A first PMOS transistor P1 is turned on when a clock signal CLK is logic low L and as such applies power voltage to a fighting node FightingN. On the other hand, the first PMOS transistor P1 is turned off when a clock signal CLK is logic high H.
When a clock signal CLK is transitioned from logic low L to logic high H at a predetermined time t1, a clock pulse signal CKP is activated after a predetermined delay d. When a clock pulse signal CKP is activated with logic high H, a first NMOS transistor N1 is turned on. Thus, an electric charge of the fighting node FightingN is discharged (indicated by a solid arrow in FIG. 3). However, due to a second PMOS transistor P2 in a latch circuit LAT, an electric charge can be provided to the fighting node FightingN (indicated by a dashed line arrow in FIG. 3).
In other words, as the first through third NMOS transistors N1 through N3 and the second PMOS transistor P2 are turned on at the same time, unnecessary power leakage can occur. In addition, since an electric charge is provided by the second PMOS transistor P2, an electric charge in the fighting node FightingN is not fully discharged in the required amount of time. Therefore, delay due to a discharging operation occurs and reliability of the clock gated circuit may decrease.
Furthermore, a discharge occurs in the fighting node FightingN if sizes of the first through third NMOS transistors N1 through N3 are larger than that of the second PMOS transistor P2. However, when the size of the second PMOS transistor P2 is larger than that of the first through third NMOS transistors N1 through N3 due to process reasons, the clock gated circuit cannot be operated.
As such, in a discharging section of the fighting node FightingN, a path for providing an electric charge to the FightingN is formed so that problems such as a waste of power, occurrence of delay, and reliability decrease result.